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EE241
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UC Berkeley EE241 B. Nikolić
EE241 - Spring 2001Advanced Digital Integrated Circuits
Lecture 10Dynamic Logic
UC Berkeley EE241 B. Nikolić
Reading� Chapter 7 by K. Bernstein� Chapter 8 by P. Gronowski� Papers from the web site on high-speed logic families
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UC Berkeley EE241 B. Nikolić
Dynamic Gates
NMOS Inverter PMOS Inverter
Courtesy of IEEE Press, New York. 2000
UC Berkeley EE241 B. Nikolić
Reliability Problems – Charge Leakage
Mp
Me
VDD
φOut
φ
ACL
(1)
(2)
φ
t
t
Vout
(b) Effect on waveforms(a) Leakage sources
precharge evaluate
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UC Berkeley EE241 B. Nikolić
Charge Leakage
Courtesy of IEEE Press, New York. 2000
ILeak = (IN sub + IN diode) – (IP sub + IP diode)
Time to switch the next gate: tsw = (CDYN * Vsw)/ILeak
Limits the minimum frequency:fmin = 1/(tsw * #phases per clk cycle)
UC Berkeley EE241 B. Nikolić
Compensating Leakage
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UC Berkeley EE241 B. Nikolić
Charge Sharing (Redistribution)
Mp
Me
VDD
φOut
φ
A
B = 0
CL
Ca
Cb
Ma
Mb
X
CLVDD CLVout t( ) Ca VDD VTn VX( )–( )+=
or
∆∆∆∆Vout Vout t( ) VDD–CaCL-------- VDD VTn VX( )–( )–= =
∆∆∆∆Vout VDDCa
Ca CL+----------------------
–=
case 1) if ∆Vout < VTn
case 2) if ∆Vout > VTn
UC Berkeley EE241 B. Nikolić
Charge Sharing - Solutions
Mp
Me
VDD
φ
Out
φ
A
B
Ma
Mb
Mbl Mp
Me
VDD
φOut
φ
A
B
Ma
Mb
Mbl
(b) Precharge of internal nodes
φ
(a) Static bleeder
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UC Berkeley EE241 B. Nikolić
Aside: Dynamic Latch
Courtesy of IEEE Press, New York. 2000
UC Berkeley EE241 B. Nikolić
Charge Sharing
A,B = 0DYN prechargedCharge sharing ifSEL toggles
Courtesy of IEEE Press, New York. 2000
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UC Berkeley EE241 B. Nikolić
Aside: Noise in ICs� Sources of noise
» Coupling– Device coupling– Capacitive coupling between wires– Inductive coupling
» Supply line bounce» Charge Injection
– From substrate– α-particles
� Robustness of a circuit» Noise margins» Sensitivity to noise
UC Berkeley EE241 B. Nikolić
Transient Response
0 0.5 1-0.5
0.5
1.5
2.5
IN &CLK
Out
Time, ns
Volta
ge
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UC Berkeley EE241 B. Nikolić
Clock Feedthrough
Mp
Me
VDD
φOut
φ
A
B
CL
Ca
Cb
Ma
Mb
Xφ
2.5V
overshoot
out
UC Berkeley EE241 B. Nikolić
Clock Feedthrough and Charge Redistribution
0 1 2 3t (nsec)
0
2
4
6
V (V
olt) φ
out
internal node in PDN
output without redistribution (Ma off)
feed
thro
ugh
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UC Berkeley EE241 B. Nikolić
Miller and Back-gate Coupling
Courtesy of IEEE Press, New York. 2000
UC Berkeley EE241 B. Nikolić
Capacitive Coupling
Courtesy of IEEE Press, New York. 2000
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UC Berkeley EE241 B. Nikolić
Capacitive CouplingDynamic node: Static node:
Courtesy of IEEE Press, New York. 2000
UC Berkeley EE241 B. Nikolić
Capacitive Coupling
Courtesy of IEEE Press, New York. 2000
Lateral coupling: Shielding
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UC Berkeley EE241 B. Nikolić
Minority Charge Injection
Courtesy of IEEE Press, New York. 2000
UC Berkeley EE241 B. Nikolić
Supply Noise
Courtesy of IEEE Press, New York. 2000
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UC Berkeley EE241 B. Nikolić
Design Considerations
Charge sharing
Ground bounce
Coupling
Leakage (Temperature dependent)
Static noise immunity (~VTH)
Clock power
Testability
Gnd
Ground bounce:
In 3
In 1
In 2
In 4
VD D
Out
CLK
CLK
UC Berkeley EE241 B. Nikolić
Cascading Dynamic Gates
Mp
Me
VDD
φ
φ
Mp
Me
VDD
φ
φ
In
Out1 Out2
φ
Out2
Out1
In
V
t
∆V
VTn
(a) (b)
Only 0→1 Transitions allowed at inputs!
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UC Berkeley EE241 B. Nikolić
Cascading Dynamic Logic
UC Berkeley EE241 B. Nikolić
Domino Logic
Mp
Me
VDD
PDN
φ
In1In2In3
Out1
φ
Mp
Me
VDD
PDN
φ
In4
φ
Out2
Mr
VDD
Static Inverterwith Level Restorer
Krambeck et al, JSSC 6/82
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UC Berkeley EE241 B. Nikolić
Logical Effort
LE =
φ
φ
In
Out
Inverter pair:
Skewed inverter pair:
UC Berkeley EE241 B. Nikolić
Logical effort
LE =
φ
φ
Out
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UC Berkeley EE241 B. Nikolić
Domino Logic - Characteristics
• Only non-inverting logic
• Very fast - Only 1->0 transitions at input of invertermove VM upwards by increasing PMOS
• Adding level restorer reduces leakage andcharge redistribution problems
• Optimize inverter for fan-out
UC Berkeley EE241 B. Nikolić
Designing with Domino Logic
Mp
Me
VDD
PDN
φ
In1In2In3
Out1
φ
Mp
Me
VDD
PDN
φ
In4
φ
Out2
Mr
VDD
Inputs = 0during precharge
Can be eliminated!
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UC Berkeley EE241 B. Nikolić
Logical Effort
LE =
φ
Out
UC Berkeley EE241 B. Nikolić
Delayed Precharge
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UC Berkeley EE241 B. Nikolić
Domino Properties� Logic evaluation propagates as falling dominoes� Evaluation period determines the logic depth� The nodes must be precharged during the precharge
period (can limit the minimum size of PMOS)� Inputs must be stable (or have only one rising
transition) during the evaluation� Gates are ratioless� Restorer is ratioed� All the gates are non-inverting� Only one transition to be optimized
UC Berkeley EE241 B. Nikolić
Multiple-Output Domino (MODL)
Hwang, Fisher, ISSCC’88
F = F1F2
Common subexpressions
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UC Berkeley EE241 B. Nikolić
Lookahead Adder
Multiple Output Domino (MODL)
Generate Propagate
UC Berkeley EE241 B. Nikolić
Lookahead Adder
4-bit group generate 4-bit group propagate
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UC Berkeley EE241 B. Nikolić
Compound Domino
Houston et al,U.S. Pat. 5,015,882May 1991.
UC Berkeley EE241 B. Nikolić
Clock-Delayed Domino