1 EE241 - Spring 2006 Advanced Digital Integrated Circuits Lecture 26: Future Perspectives 2 Embedded Software-Based Self-Testing for Programmable System Chips BusInterface Master Wrapper Bus Arbiter Low-Cost Tester Test program Responses VCI Signatures DSP VCI IP Core VCI System Memory VCI On-chip Bus BusInterface Master Wrapper BusInterface Target Wrapper BusInterface Target Wrapper Loading test program at low speed Self-test at operational speed Unloading response signature at low speed Low-cost tester High-quality at-speed test Low test overhead Non-intrusive Test in normal operational mode No violation of power consumption More accurate speed-binning CPU
Transcript
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EE241 - Spring 2006Advanced Digital Integrated Circuits
Lecture 26:Future Perspectives
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Embedded Software-Based Self-Testing for Programmable System Chips
Length of presentation: 8 + (N-1) *2 minutes (with N number of people in group)
3’ per group allocated for Q&A
Presentation should contain the following
1 slide outlining problem
Couple of slides discussing proposed solution and how it differs from what other people have done
Couple of results slides
Number of slides should NOT be larger than the number of minutes
BE CONCISE and DO NOT EXCEED THE ALLOTTED TIME
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Project ReportsDue by Fr May 12th 5pmShould be in paper format – max of 6 pages (font 10 minimum)
Title of the project/ your names and e-mail addresses Abstract (100 words) Motivation Problem statement Possible solutions from literature (from midterm report) Proposed comparison/solution. Discuss why did you select this particular one. Conditions/assumptions of your design Analysis: Does it work? Analytical analysis, simulation results.Conclusion. What is this approach good for? What else could be done? References
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5
Take-Home Final
Two options:Early Bird: Fr May 12, 5pm – Monday May 15, 10amRegular Offering: Monday May 15, 5pm – Th May 18, 10amSend e-mail to [email protected] and [email protected] if you want to subscribe to the early bird option
Submissions of answers preferred in electronic form (scans are ok). If impossible, paper version to Jessica in 558 Cory before 10am on respective days.THIS IS A PRIVATE AND PERSONAL EXERCISE. Honesty is appreciated.
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Semester Look Back
What we did not cover …Interconnect
Key challenge
Interesting areas: high-speed serial interconnect, alternative interconnect, networks on a chip
Arithmetic
Trading off performance and power
Please send feedback on topics you would like to see covered in less or more detail
…that exhibit macro-regularitywhen assembled at chip-level
2-D FFT plotsof poly-Si
patterns
ASIC “spatial” regularity2-D FFT plots
of poly-Si patterns
Brick “spatial” regularity
[Courtesy: Larry Pileggi, Andrzej Strojwas, CMU – C2S2]
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A Roadmap for Late-Silicon Age Design
• Regularity and Structure
• Concurrency and Flexibility
• Self-Healing
• Error-Resiliency
• Embracing Randomness
Immediate future
Immediate future
Concurrency and heterogeneity::• Driven by power density concerns• Alternative to higher clock frequencies
Flexibility:• Higher re-use, shorter time-to-market, in- field adaptation and upgrade
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The Age of Concurrency and Flexibility
AMD Dual Core Microprocessor
Heterogeneous concurrency now prevalent in wireless, automotive,consumer, media processing, graphics and gaming
Heterogeneous concurrency now prevalent in wireless, automotive,Heterogeneous concurrency now prevalent in wireless, automotive,consumer, media processing, graphics and gamingconsumer, media processing, graphics and gaming
Berkeley BEE-II: 2 TOPs system protytyping environment
• Compilers, operating systems, architectures are definitely not!• How to do research on 1000 CPU systems in compilers, OS, architecture “in parallel”?
30-40 TOPS (2 TFlops) Rack
One Solution: RAMPA Framework for Multi-Core System Development• Create 1000-CPU system from ~ 40 FPGAs• Distribute out-of-the-box Massively Parallel Processor that runs standard binaries of OS and application to all major research institutes in the US.• Provides uniform framework for architecture development and exploration
Core Team: D. Patterson, J. Warzyniek, J. Rabaey (UCB), James Hoe (CMU), Christos Kozyrakis (Stanford),Krste Asanovich (MIT), M. Oskin (Washington), D. Chiou (Texas), W. Hwu (Illinois), S. Lu (Intel)
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A Roadmap for Late-Silicon Age Design
• Regularity and Structure
• Concurrency and Flexibility
• Self-Healing
• Error-Resiliency
• Embracing RandomnessLater this decade
Later this decade
Self-Healing Architectures• On chip-test and diagnostics used to
correct for variations and stress• Static and dynamic
Dynamically adjust supply and threshold design parameters to center the design in the presence of process variations!
Courtesy: K. Cao, Berkeley
10xEasier Again in Regular Fabrics
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Adaptive (Body) Biasing Impact
Courtesy: P. Gelsinger and S. Borkar, Intel (DAC04)
4.5 mm
5.3
mm
Multiplesubsites
4.5 mm
5.3
mm
Multiplesubsites
4.5 mm
5.3
mm
Multiplesubsites
4.5 mm
5.3
mm
Multiplesubsites
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Dynamic Resource Allocation
In the MultiIn the Multi--Processor SpaceProcessor SpaceCompiler combines load Compiler combines load assignment with DVSassignment with DVS
mdlmdl group at PSUgroup at PSU
405060708090
100
2 4 8 16 32
Num ber of Processors
Nor
mal
ized
Ene
rgy
3D DFE LU SPLAT MGRID WAVE5
More savings with more processors!More savings with more processors!
In the Interconnect SpaceIn the Interconnect SpaceUse routing throttling to Use routing throttling to perform thermal managementperform thermal management
A “pseudo-synchronous”approach to address process variations and power minimization with minimal overhead by combining circuit and architectural techniques
Courtesy: T. Austin, D. Blaauw, MichiganCourtesy: T. Austin, D. Blaauw, Michigan
Example: Aggressive Deployment using “Razor”Example: Aggressive Deployment using “Razor”
recover
IF
Razo
r FF
ID
Razo
r FF
EX
Razo
r FF
MEM(read-only)
WB(reg/mem)
errorbubble
recover recover
Razo
r FF
Stab
ilizer
FF
PC
recover
flushID
bubble
errorbubble
flushID
errorbubble
flushID
FlushControl
flushID
error
recover
IF
Razo
r FF
Razo
r FF
ID
Razo
r FF
Razo
r FF
EX
Razo
r FF
Razo
r FF
MEM(read-only)
WB(reg/mem)
errorbubble
recover recover
Razo
r FF
Razo
r FF
Stab
ilizer
FF
Stab
ilizer
FF
PCPC
recover
flushID
bubble
errorbubble
flushID
errorbubble
flushID
FlushControl
flushID
error
“razored pipeline”“razored pipeline”
Shadow Latch
Error_L
Errorcomparator
clk_del
FF
clk
QD
Processor
Total
Optimal Voltage
RecovEnergy
Supply Voltage
Ene
rgy
Processor
Total
Optimal Voltage
RecovEnergy
Supply Voltage
Ene
rgy
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“Aggressive” Deployment At the Algorithm Level
][nx][nyaMain Block
Estimator
][ˆ ny| | >Th
][nye
Energy savings
Voltage
Pow
er
Pmain
PTOT
PEC
1.0
1.0
Courtesy: N. Shanbhagh, IllinoisCourtesy: N. Shanbhagh, Illinois
Voltage overscale Main Block.
Correct errors using Estimator.
Power savings ≥ 3X!
Voltage overscale Main Block.
Correct errors using Estimator.
Power savings ≥ 3X!
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• Core function validated by checker
• Checker relaxes burden of correctness on core processor
• Core does the heavy lifting, removes hazards that could slow the simple checker
IntraIntra--thread thread Control FlowControl Flow
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Towards malleable, resilient architectures
The Quest: Scaleable (hard and soft) architectures that provide flexible redundancy to accommodate systematic and random, static and dynamic errors while avoiding brittleness!
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A Roadmap for Late-Silicon Age Design
• Regularity and Structure
• Concurrency and Flexibility
• Self-Healing
• Error-Resiliency
• Embracing Randomness
The Far Beyond
The Far Beyond
Maintaining a purely deterministic Boolean abstraction ultimately becomes untenable! Maintaining our abstractions == Slowly abandon them !!
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The Search for (New) Scaleable and Stackable Abstractions
An Interesting Case Study:The “Neural Network” MOCProperties:Properties:• Works well on noisy signals• Uses “soft” decisions • Operates in the presence of failures of components and interconnections
Challenge: Limited scopeWorks mostly for classification problems
Artificial neuronArtificial neuron
Allow devices to make errorsand use models-of-computation that tolerate them
(signal processing, communication, coding, information theory)
Example: A configurable radio architecture based on collaborative autonomous entities
Source: J. Roychowdhury, J. Rabaey
Array of locally-coupled cheaplow-power oscillator-based units• Known to exhibit complex, spontaneous pattern formation • Operation mode selected through choice of coupling factors and operational nodes
