© 2010 Grandis Corporation
Latest Advances andFuture Prospects of STT-RAM
Alexander Driskill-SmithGrandis, Inc.
Non-Volatile Memories WorkshopUniversity of California, San Diego
April 11–13, 2010
4/12/2010 1
© 2010 Grandis Corporation
Outline
4/12/2010 2
• Grandis Corporation Overview
• Introduction to STT-RAM*
• Latest STT-RAM Device & Chip Results
• STT-RAM Market & Applications
• Conclusions
*STT-RAM: Spin Transfer Torque Random Access Memory
© 2010 Grandis Corporation
Grandis Corporation Overview
• Grandis develops & licenses STT-RAM proprietary NVM solutions– Grandis’ non-volatile STT-RAM enables a wide variety of low-cost and high-performance
memory products at the 45 nm technology node and beyond
• Incorporated in Delaware in 2002
• Top-tier VC Funded– Sevin Rosen, Applied Ventures, Matrix
Partners, Incubic, Concept Ventures
• Headquarters: Silicon Valley, CA– R & D Offices: California, Japan, S. Korea
• Strong & broad STT-RAMpatent portfolio and know-how – 52 patents granted to date in U.S.– Total 193 patents filed and 63 granted worldwide
• Our mission is to establish Grandis STT-RAM as the #1 choice for memory solutions beyond 45 nm
34/12/2010
STT-RAM: Spin Transfer Torque Random Access Memory
© 2010 Grandis Corporation
Grandis Milestones in STT-RAM
2002: Grandis files first key patents in STT-RAM
2004: Grandis reports world’s first STT switching in MTJs
2005: Renesas Technology of Japan licenses Grandis IPand begins developing STT-RAM for embedded applications
2007: Grandis receives Technology Innovation Award from Frost & Sullivan
Grandis wins NIST ATP award ($2M / 3 yrs) to develop STT-RAM
2008: Hynix Semiconductor of Korea licenses Grandis IPand begins developing STT-RAM for standalone applications
Grandis wins DARPA contract ($15M / 4 yrs) to develop STT-RAM
2009: Grandis upgrades MTJ Fab to handle 300 mm customer wafers
Grandis wins two additional NSF Grants worth $1M
Grandis awarded its 50th patent in the U.S.
2010: Grandis achieves DARPA Phase I development milestones 6 months early
44/12/2010
© 2010 Grandis Corporation
Grandis Development Partners
54/12/2010
© 2010 Grandis Corporation
The Need for a New Memory Technology
• All existing memory technology is greatly challenged beyond 45 nm– SRAM: high power consumption, leakage increasing 10X with each technology node– DRAM: refresh current increasing, incompatible process for embedded applications– Flash: limited endurance, high write power, very slow write speed, MLC & aggressive
scaling leading to reduced performance and complicated controller
• Power consumption in both mobile and data center applications is now a real issue– Incorporating STT-RAM in mobile applications can dramatically reduce standby power– Replacing DRAM with STT-RAM in data centers can reduce power by up to 75%
• Memory performance is fast becoming the key bottleneck that limits system performance– Critical applications are becoming more data-centric, less compute-centric– Instant-on is becoming a requirement for many applications
• These problems create an opening for an alternative, high-density, high-speed, non-volatile random access memory
64/12/2010
© 2010 Grandis Corporation
The Solution: STT-RAM Universal Memory
• STT-RAM is an evolution in magnetic storage from hard disk drives to solid-state semiconductor memory– Uses spin-polarized current (“spintronics”) to write magnetic bits– Non-volatile, random-access memory with no moving parts– Key building block is the magnetic tunnel junction (MTJ)
• STT-RAM has all the characteristics of a universal memory – Non-volatile– Highly scalable– Low power consumption– SRAM read/write speed– Unlimited endurance– DRAM & Flash density (6 F2)– Multi-level cell capability
• STT-RAM uses existing CMOS technology with 2 additional masks and less than 3% cost adder
74/12/2010
© 2010 Grandis Corporation
Key Advantages over conventional MRAM:
• Excellent write selectivity <— Localized spin-injection within cell• High scalability <— Write current scales down with cell size • Low power consumption <— Low write current (<100 μA)• Simpler architecture <— No write line, no by-pass line and no cladding• Faster operation <— Multibit (parallel) writing compatible
Conventional MRAM Cell
Write Current: Isw ~ 1 / Volume
STT-RAM Cell
Isw ~ Volume
STT-RAM versus Conventional MRAM
84/12/2010
© 2010 Grandis Corporation
STT Write Mechanism
• Spin-transfer torque writing– Uses spin-polarized current instead of
magnetic field to switch magnetization of storage layer
– Has low power consumptionand excellent scalability
94/12/2010
MTJ (magnetictunnel junction)
© 2010 Grandis Corporation
STT-RAM Key Parameters
• Jc0 (write current density) => cell size, write speed• TMR (read signal) => sense margin, read speed• Δ (thermal stability) => data retention, read disturb, memory size, temperature range• Vbd (MTJ breakdown voltage) => lifetime, endurance
• Key challenge is achieving low STT writecurrent density and high thermal stabilityat the same time
• Write current:
• Thermal stability:
104/12/2010
STT-RAM Cell
...,2
20 ++=⎥⎦
⎤⎢⎣⎡ += shapeIntrisicK
dK
FSc HHHHHetAMI
hηα
TkAtM
TkAtM
B
FS
B
FS22
K
2 H
∝=Δ
Assuming intrinsic anisotropy is much smaller than shape anisotropy
© 2010 Grandis Corporation
Latest MTJ Device Results
• New class of in-plane MTJ structures with high partial perpendicular are excellent for maintaining thermal stability as device sizes shrink
• Average write current density Jc0 for advanced MTJs is in range 1–2 MA/cm2
– Dual barrier MTJ (DMTJ) devices provide the lowest average write current density of ~1 MA/cm2
AP-P P-APHigh partial perpendicular anisotropy (>80% of 4πMs)
4/12/2010 11
FL
PL
PL
2 MTJ barriers
DMTJ
Each Jc0 data point is obtained statistically by fitting write current vsdevice area data from thousands of MTJs over a wide range of device sizes
© 2010 Grandis Corporation
STT-RAM Scalability
• New micromagnetic simulations show in-plane STT-RAM scalable beyond 20 nm– Key issue is maintaining thermal stability as device area shrinks (e.g. by increasing free layer
thickness or aspect ratio)
4/12/2010 12
Simple Scaling In-planeSTT-RAM
PerpendicularSTT-RAM
Write current Ic ~w2 ~w2
Thermal stability Δ ~w ~w2
Scaling at Fixed Δ In-planeSTT-RAM
PerpendicularSTT-RAM
Write current Ic ~w3/2 Constant
Thermal stability Δ Constant Constant
Scaling atFixed Δ = 60
Simple Scaling
© 2010 Grandis Corporation
STT-RAM Minimum Cell Size
• 6 F2 minimum cell size with shared source line architecture– Minimum 1 F gate width transistor can drive 6 F2 cell beyond 45 nm
• Future multi-level cell and cross-point architectures will enable further scaling beyond 6 F2
134/12/2010
2 MA/cm2
1 MA/cm2
Transistor
© 2010 Grandis Corporation
Grandis STT-RAM Chip
• The most advanced STT-RAM prototype chip in the industry
Higher density chips at 54 nm & beyond are in development
144/12/2010
• Fully-functional
• 256 kbit capacity
• 90 nm CMOS
• 4 Cu metal process
• LP high reliability CMOS
• Write current <200 µA
• Write/read speed 20 ns
• Endurance >1013
© 2010 Grandis Corporation
STT-RAM Resistance Distribution
4/12/2010 15
• Large separation between resistance states and small process distribution provide excellent read characteristics– TMR (Tunneling Magnetoresistive) signal ~100%– Rlow distribution sigma 4% (1σ), Rhigh distribution sigma 3% (1σ)– Rhigh – Rlow separation = 20σ
Rlow“0” state Rhigh
“1” state
© 2010 Grandis Corporation
STT-RAM Write Voltage Distribution
• Mean write voltage ~1.15 V– Includes voltage across both
transistor and MTJ
• Write voltage distribution ~3% (1σ) or ~9% (3σ)
• Grandis target write voltage distribution <15% (3σ)
164/12/2010
© 2010 Grandis Corporation
STT-RAM Endurance
4/12/2010 17
• Unlimited write endurance (>1016 cycles) projected from TDDB tests with stressed voltage and temperature– 1013 endurance demonstrated to date under real operating conditions
© 2010 Grandis Corporation
STT-RAM Market Evolution & Size
• Grandis STT-RAM will be in production in <2 years– Initially, as an embedded SRAM & low power mobile RAM replacement– In medium term, as a DRAM & NOR flash replacement– Ultimately, as a storage class memory that can replace NAND Flash
• STT-RAM total addressable market will be >$80B by 2015
184/12/2010
CPU
SRAM
DRAM
Flash
HDD
STT-RAMLowest
costFastestspeed
© 2010 Grandis Corporation
Mobile RAM Application
• STT-RAM can replace MCPs in mobile applications with a single chip– Non-volatile, higher-speed, lower power consumption, and lower cost
194/12/2010
Handset SolutionSharp 922SH
Multi-Chip Package (MCP)(ST M39PNRA2A)
NOR: STMicro 512Mb 2pcs
NAND: Hynix 2Gb SLC(single-level-cell)1Pcs
DRAM: Elpida 512Mb DDR2 SDRAM 2Pcs
STT-RAM
© 2010 Grandis Corporation
Smart Phone with Conventional Memory
204/12/2010
x16 (mux)
Baseband/Modem
Application ProcessorRF
MMC/ SD
Audio/ Video/ TVout
Memory Cntrl
NORPSRAM
MCP
LP-DDR
x16/x32
NANDSLC/MLC
MCP
NOR
Memory Cntrl
x16(mux) x8/x16
Serial i/f
Store & run
radio protocol
stack
on-chip level 1(2) cache sizes are a function of ext. memory access latency and required
bandwidth
Media Processor
FRAMEBUFFER(LP-SDR
e.g. 64Mb)
SiP
LCDDisplay
ARM9
Imagesensor
© 2010 Grandis Corporation
Smart Phone with STT-RAM Memory
214/12/2010
x16 (mux)
Baseband/Modem
Application ProcessorRF
MMC/ SD
Audio/ Video/ TVout
Memory Cntrl
STT-RAM
x16/x32
NANDSLC/MLC
MCP
STT-RAM
Memory Cntrl
x16(mux) x8/x16
Serial i/f
Store & run
radio protocol
stack
on-chip level 1(2) cache sizes are a function of ext. memory access latency and required
bandwidth
On-chip STT-RAM
Frame Buffere.g. 64Mb)
LCDDisplay
ARM9
Imagesensor
Media Processor
© 2010 Grandis Corporation
SRAM DRAM Flash(NOR)
Flash (NAND) FeRAM MRAM PRAM RRAM STT-
RAM
Non-volatile No No Yes Yes Yes Yes Yes Yes Yes
Cell size (F2) 50–120 6–10 10 5 15–34 16–40 6–12 6–10 6–20
Read time (ns) 1–100 30 10 50 20–80 3–20 20–50 10–50 2–20
Write / Erase time (ns) 1–100 15
1 μs /10 ms
1 ms /0.1 ms
50 / 50 3–20 50 / 120 10–50 2–20
Endurance 1016 1016 105 105 1012 >1015 108 108 >1015
Write power Low Low Very high Very high Low High Low Low Low
Other power consumption
Current leakage
Refresh current None None None None None None None
High voltage required No 3 V 6–8 V 16–20 V 2–3 V 3 V 1.5–3 V 1.5–3 V <1.5 V
Existing products Prototype
Memory Technology Comparison
224/12/2010
© 2010 Grandis Corporation
Intensified Worldwide Interest in STT-RAM
Jun. 2009: NEC tips new MRAM technology using STT at VLSI conference,expects it to be scalable beyond 55 nm process
Oct. 2009: Crocus Technology announces it will transition to STT-RAM fromits existing heat-assisted TAS-MRAM in 2010
Nov. 2009: Korean Government updates on progress of $50MSTT-RAM program with Samsung and Hynix, installs300 mm STT-RAM facility at Hanyang University
Dec. 2009: TSMC and Qualcomm describe 45 nm low powerembedded STT-RAM process and design at IEDM
Dec. 2009: Also at IEDM, Hitachi & Tohoku University presentMTJ SPICE model, and Intel presents design space studyand requirements for STT-RAM in embedded applications
Dec. 2009: France launches €4.2M SPIN project with 11 partners including LETI,Spintec & Crocus, one of project goals is to develop magnetic FPGAs
Jan. 2010: Everspin introduces 1 Mb MRAM for RAID storage applications
Jan. 2010: Toshiba achieves 9 µA switching current in perpendicular STT-RAM
Feb. 2010: Toshiba describes a 64 Mb STT-RAM using perpendicular MTJsand 65 nm CMOS at ISSCC conference, Fujitsu also presents a paper
4/12/2010 23
© 2010 Grandis Corporation
Conclusions
4/12/2010 24
• Spintronics (spin electronics) is a rapidly emerging field– STT-RAM and spin logic will have a significant impact on technology in the 21st century,
enabling a new era of instant-on, high-speed portable devices with extended battery life
• STT-RAM has a huge potential market as a universal, scalable memory– It can replace eSRAM & eFlash at 45 nm, DRAM at 32 nm, and ultimately replace NAND
Flash as a storage class memory at 22 nm and beyond
• Worldwide STT-RAM development has increased significantly– Government programs in the United States (DARPA), Korea, Japan & France– IBM, Qualcomm, Intel, Everspin, TSMC, Hynix, Samsung, Renesas, NEC, Toshiba,
Hitachi, Fujitsu, …
• Grandis is focused on commercializing STT-RAM in 1–2 years– It has the key fundamental and blocking patents in STT-RAM, and has early strategic
partnerships in product development with key semiconductor memory players
• Much progress has been made, but still plenty of room for innovation
© 2010 Grandis Corporation
Please visitwww.GrandisInc.com
for more information
254/12/2010
