JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.1, FEBRUARY, 2016 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/JSTS.2016.16.1.031 ISSN(Online) 2233-4866

Manuscript received Apr. 26, 2015; accepted Oct. 26, 2015 Department of Electronics and Computer Engineering, Hanyang Univ., Seoul, Korea E-mail : yhsong2008@hanyang.ac.kr

Novel Self-Reference Sense Amplifier for Spin-Transfer-Torque Magneto-Resistive Random Access Memory

Jun-Tae Choi, Gyu-Hyun Kil, Kyu-Beom Kim, and Yun-Heub Song

Abstract—A novel self-reference sense amplifier with parallel reading during writing operation is proposed. Read access time is improved compared to conventional self-reference scheme with fast operation speed by reducing operation steps to 1 for read operation cycle using parallel reading scheme, while large sense margin competitive to conventional destructive scheme is obtained by using self-reference scheme. The simulation was performed using standard 0.18 mm CMOS process. The proposed self-reference sense amplifier improved not only the operation speed of less than 20 ns which is comparable to non-destructive sense amplifier, but also sense margin over 150 mV which is larger than conventional sensing schemes. The proposed scheme is expected to be very helpful for engineers for developing MRAM technology. Index Terms—Magneto-resistive Random Access Memory, MRAM, self-reference, sense amplifier, operation speed, sense margin

I. INTRODUCTION

STT-MRAM is one of the most promising candidates for universal memory because of its non-volatility, high speed, high endurance and low power consumption. STT-MRAM uses Magnetic Tunnel Junction (MTJ) for storing data, which is consisted of an insulating layer between two ferromagnetic layer, which one of them is

called pinned ferromagnetic layer since the magnetization is fixed to one direction, and the other is called free ferromagnetic layer since the magnetization direction can be switched. According to the magnetization direction of these two layers, MTJ stores 1 (Anti-parallel state, AP, high resistance) and 0 (Parallel state, P, low resistance). Fig. 1 shows the R-V characteristic of MTJ. The resistance ratio between two states is called Tunnel Magneto-resistance Ratio (TMR), and can be obtained by Eq. (1)

AP P

P

R RTMRR-

= (1)

MRAM read operation compares the resistance

difference between AP and P state to read the stored data. To distinguish the data stored in the MTJ, a reference between the two states is required. MTJ state is determined by comparing the resistance of MTJ with reference resistance. When MTJ is AP (P) state, the resistance of MTJ is higher (lower) than the reference, which leads the output value “1” (“0”) [1].

Fig. 1. R-V characteristics and resistance variation of MTJ.

32 JUN-TAE CHOI et al : NOVEL SELF-REFERENCE SENSE AMPLIFIER FOR SPIN-TRANSFER-TORQUE MAGNETO-RESISTIVE …

However, MTJ resistance strongly depends on the process variation, such as oxide thickness and interface uniformity, and experimental circumstances, such as temperature and bias voltage [2]. Fig. 2(a) shows various parameters affecting resistance and TMR, and Fig. 2(b) MTJ resistance dependence on them. As shown in Fig. 2(b), it is hard to set reference value between RP and RAP since the resistance shows broad variation according to oxide thickness (tox), cell area (A), temperature (T) and bias voltage (Vb) variation. Since the RP variation leads to TMR variation, RAP resistance shows wider distribution compared to RP resistance. Resistance variation according to various factors makes it difficult to set proper reference value. To overcome this issue, various types of self-reference scheme have been proposed [3-5]. There are two kinds of self-reference read schemes, destructive [3, 4] and non-destructive self-reference [5]. Destructive self-reference sense amplifier guarantees high sense margin, but the operation speed is

slow since they require 4 cycles for reading. To overcome the speed issue of destructive reading, non-destructive self-reference sense amplifiers are proposed. The scheme enabled enhanced operation speed compared to destructive schemes by using self-reference with not changing the cell data and comparing the slope of the bias-dependent resistance slope according to bias voltage. However, since non-destructive scheme uses the bias dependent slope of resistance according to MTJ state when biased with different voltage, they provide relatively small sense margin compared to destructive schemes.

In this work, we propose a Parallel Reading Sense Amplifier (PRSA) scheme. PRSA scheme uses destructive self-reference method to ensure large sense margin, and enhanced the operation speed by using parallel read and write operation. The proposed PRSA provides not only fast operation speed which is competitive to non-destructive scheme, but also high sense margin which is competitive to destructive scheme.

Section II explains several types of self-reference sense-amplifiers. Section III shows the schematics and operation of the proposed sense-amplifier. Section IV and V show the simulation descriptions and results of proposed scheme and simulation results. Finally, Section 6 shows the conclusion.

II. SELF-REFERENCE SENSE-AMPLIFIER

There are several types of self-reference sense-amplifiers that have been proposed, which are mainly divided to two types, destructive and non-destructive read according to operation steps.

There are two types of destructive self-reference read proposed by G.T. Jeong in 2003 [3] and H. Tanizaki in 2006 [4]. Since destructive schemes compare the stored state and changed state of the MTJ cell itself, it can provide best sense margin. However, since the read operation requires 4 steps for 1 read cycle, first read, writing “0 / 1”, second read and write back in both SA scheme, read operation requires comparably long operation time, which gives an operation speed disadvantage. Even though large sense margin is a great advantage, low-speed operation is more critical issue for universal memories.

To overcome the speed disadvantage of destructive

(a)

(b)

Fig. 2. (a) Parameters affecting MTJ resistance, (b) experimental results of RP and RAP distribution according to increasing temperature.

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scheme, Y. Chen proposed non-destructive scheme in 2010 [5]. Non-destructive scheme only requires 2 steps for 1 read cycle, which enables to overcome the speed limitation of destructive scheme. However, non-destructive scheme compares the slope difference of resistance (ΔRH and ΔRL) according to the state of MTJ, which leads to small sense margin compared to

To increase the competitiveness of STT-MRAM, it is necessary to enhance the operation speed while maintaining sufficient sense margin. In this paper, we propose a destructive scheme with operation speed comparable with non-destructive scheme and sense margin comparable with conventional destructive schemes.

III. CIRCUIT DESCRIPTION

1. Parallel Reading Sense Amplifier In this section, we propose Parallel Reading Sense

Amplifier (PRSA) with competitive operation speed and enhanced sense margin. The term parallel reading refers to the operation method which 1st read operation takes place during the initial phase of write operation at the same time. Fig. 3 shows the comparison of process flow and operation timing diagram between destructive, non-destructive and PRSA scheme. As shown in Fig. 3, PRSA can reduce the access time while securing sufficient sense margin by reducing the required operation steps of destructive reading scheme to only 2 cycles.

Fig. 4 shows the current (IC) versus switching time (tPW) characteristics of MTJ. As shown in Fig. 4, there are two main switching regions, precesional and thermally assisted switching. In precesional region, required current increases dramatically to reduce the switching time, and in thermal assisted region, required current slowly increases while reducing the switching time. Proposed PRSA use the characteristic that the switching time can be controlled by adjusting the amount of current through MTJ [6, 7].

2. PRSA Schematics and Operation

Fig. 5 shows the full schematics of PRSA. As shown

in the figure, full circuit PRSA is composed of MTJ

(a)

(b)

Fig. 3. (a) Comparison between operation steps of destructive schemes (top left), non-destructive schemes (top right) and PRSA scheme (bottom), (b) timing diagram comparison for destructive scheme and PRSA scheme.

Fig. 4. Switching time (Pwidth) – Switching current (Ic0) characteristics of MTJ.

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arrays, Write Driver (WD), input node, sense amplifier (SA), control driver (CD) and output node. We used top pinned structure MTJ model for the simulation. The CD controls the direction of the current by CBL and CSL signal according to DIN signal (input signal from input pin for storing data) and Dout (output signal) when WL turns on, and the CLP signal controls the bit-line clamp write-back operation. The input node is a bridge between MTJ array and SA, and controls input IN and INb according to switch (SW) signal and CLP. WD flow current with different direction according to read, write and write-back operation using the signal CBL and CSL from CD. Fig. 6 and 7 shows schematics and timing of two main circuits of PRSA, Control driver and sense amplifier. Fig. 6 shows the schematics and timing diagram of control driver. The control driver controls input circuit and write driver (WD) by input signal DIN, Dout and VWL. As VWL becomes high state, control circuit senses the DIN, Dout and VWL. When MTJ is initially in P state, DIN is high and Dout is low, the control circuit output WAP, WP and CLP becomes high, low and high, respectively, which control the input circuit to flow current toward AP writing current direction. When the MTJ state changes from P state to AP state, DIN is still high and Dout switches to high state, and the control circuit output WAP, WP and CLP switches to low, high and low, respectively, and the input circuit current direction changes from AP writing current to P writing current for writing back operation of original stored data (Pstate). On the other hand, when MTJ is initially AP state, DIN is high and Dout is low, the control circuit output WAP, WP and CLP becomes high, low and high, respectively, which control the input circuit to flow current toward AP writing current direction. During the

read operation, MTJ do not change its state since MTJ state is originally AP state, and AP writing current flows through the MTJ. Therefore, WAP, WP and CLP becomes high, low, and high, respectively, and the control circuit controls the input circuit to keep flowing current to AP writing direction until the VWL turns off.

Fig. 7 shows the schematics and timing diagram of sense amplifier. The aspect ratio of MIN and MINb to get sufficient and stable sense margin should be larger than 1 as shown in (2),

1MINb

MIN

WLWL

æ öç ÷è ø >æ öç ÷è ø

(2)

From the control driver output, input driver is enabled

to flow current to AP writing direction when WL, SAE and BIAS_p is turned on.

As current flow through the MTJ, switch SW is closed to store initial VBL in C1 and opens to keep the input INb to initial VBL. The capacitance of C1 is 11.069 fF, and it

Fig. 5. Full circuit schematic proposed PRSA.

(a)

(b)

Fig. 6. (a) Schematics, (b) operation timing diagram of PRSA control circuit.

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can be chosen between 10~25 fF. Capacitance over 30 fF brings large delay time and less than 10 fF brings large noise signal. SW is closed for very short period during the initial phase while AP writing current (Pinned to Free layer direction) flows through the MTJ, and while SW is closed, the BL voltage which is VMINb biased to the gate of MINb is stored in C1. When MTJ is initially P state, the VMIN (MIN gate voltage)maintains the same voltage with VMINb (MINb gate voltage) until MTJ changes to AP state, which makes Vb higher than Va before MTJ switches to AP state due to transistor aspect ratio

difference. When the MTJ changes to AP state, the voltage VMIN goes up, which leads to Vb drop lower than Va since high VMIN enables MIN to flow larger current after MTJ switching, and Dout is determined to be high representing data 0. After data is determined to be 0, the WD performs write-back operation by flowing P-writing current (Free to Pinned layer direction). On the other hand, when MTJ is initially AP state, VMIN maintains the same voltage with VMINb during the read operation period since MTJ state do not change, which makes Vb higher than Va during read operation period, and Dout is determined to be low representing data 1. For PRSA to sense the stored data more accurately, the aspect ratio between MIN and MINb should be precisely determined satisfying Eq. (2).

IV. SIMULATION DESCRIPTION

To perform the circuit simulation with MTJ cell, we

used a MTJ Macro-model based on experimental results using Verilog-A language which can interact with Hspice tool to realize the MTJ characteristics for circuit simulation. We have set the parameters such as oxide thickness (1 nm), cell dimensions (40 nm diameter) and other factors used in Macro-models to target CoFeB-MgO based p-MTJ sample proposed by S. Ikeda in 2010 [8].

Fig. 8 shows the simulation results of resistance variation of MTJ with 10,000 Monte-Carlo simulations at temperature of 300 K. As shown in the Fig. 8(a), median RP, RAP and TMR values are 14 kΩ, 32 kΩ and 128%,

(a)

(b)

Fig. 7. (a) Schematics, (b) operation timing diagram of PRSA sense amplifier.

Fig. 8. Simulation results of resistance variation of MTJ with 10,000 Monte-Carlo simulations.

36 JUN-TAE CHOI et al : NOVEL SELF-REFERENCE SENSE AMPLIFIER FOR SPIN-TRANSFER-TORQUE MAGNETO-RESISTIVE …

respectively. By performing 2% oxide variation and 10 % TMR variation using Monte-Carlo simulations, RP variation from 8 kΩ to 21.7 kΩ, RAP variation from 8.6 kΩ to 62.9 kΩ, and TMR variation from 7.5 to 190 % were achieved during the circuit simulation.

Circuit simulation is performed by Hspice simulation tool with standard 0.18 mm CMOS process. NMOS and PMOS have length of 180 nm, and width of 360 nm and 720 nm each. MTJ switching delay is set to be 10 ns by controlling the writing current through the MTJ during read operation. Switch SW is set to be closed with the VWL is turned on, maintain closed state for 2 ns to charge the C1, than open to keep the stored data.

V. SIMULATION RESULTS

Fig. 9 shows the simulation results of 20 operation cycles with MTJ characteristics with oxide thickness and TMR variations with Monte-Carlo samples while the initial MTJ was P state. MTJs which are initially AP state is not shown in the simulation results since read error or failure occurs only when initial MTJ state is parallel during read operation. As shown in the Fig. 9, we confirmed that the operation time is less than 20 ns assuming that the MTJ switching time is 10 ns, which is much faster than previous destructive schemes which shows about 150 ns [3] and 80 ns [4], respectively. The read access time is rather fast enough to be compared with non-destructive scheme, which shows about 15 ns [5]. Moreover, the read access time can be reduced or increased according to its application by controlling the switching delay time with the precisely current

adjustment. Fig. 10 shows the simulation results of PRSA voltage

sense margin (VSM) from 10,000 Monte-Carlo simulations with temperature of 300 K and 363 K, where, VSM shows the voltage difference between VIN and VINb. As shown in the figure, the sense margin of about 150 mV is obtained while reducing the read access time to 20 ns. From these results, we confirmed that PRSA improved the sense margin about twice compared to conventional self-reference schemes, which has sense margin of 80 mV [4, 5]. Table 1 summarizes the parameters used and simulation results.

VI. CONCLUSIONS

We proposed PRSA which provides competitive speed and sense margin. To improve the speed and sense margin at once, destructive sensing scheme is selected while reducing the operation steps and performing read operation in real time. From the simulation results, we confirmed that the PRSA operation shows fast speed less than 20 ns, which is suitable for universal memory, and obtained competitively large sense-margin over 150 mV. Moreover, read operation speed would be able to be

Fig. 9. Simulation results of PRSA with MTJ parameter variation.

Table 1. Summary of simulation conditions and resultsProcess 0.18 mm CMOS

tox 1 nm (variation 2%) RP 14 kΩ (8 < RAP < 21.7 kΩ) RAP 32 kΩ (8.6 < RAP < 62.9 kΩ)

MTJ Macro-model

TMR 128 % (7.5 < TMR < 190 %) Operation speed Less than 20 ns

Sense margin Over 150 mV Read failure 0

Fig. 10. Simulation results of voltage sense margin from 10,000 Monte-Carlo simulations.

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enhanced even more and larger sense margin could be obtained if MTJ with faster switching time and higher TMR is developed,. We expect that the proposed scheme would be very helpful for engineers for studying and developing MRAM technology.

ACKNOWLEDGMENTS

The authors would like to thank C.-K. Kim of the DRAM design team, Memory Division, Samsung Electronics Co., Ltd. for his support and helpful discussions. This research was supported by the MOTIE (Ministry of Trade, Industry & Energy (10044608) and by the KSRC (Korea Semiconductor Research Consortium) support program for the development of future semiconductor devices. And, it was also supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning (NRF-2015R1A2A2A01007289).

REFERENCES

[1] S. Yuasa, et al, “Giant room-temperature magnetoresistance in single-crystal Fe/MgO/Fe magnetic tunnel junction,” Nature materials, 2010, Vol 3, pp. 868-871, Dec. 2010.

[2] Y. Lu, et at., “Bias voltage and temperature dependence of magnetotunneling effect,” Journal of Applied Physics, Vol. 83, No. 11, pp. 6515-6517, Jun. 1998.

[3] G. Y. Jeong, et al, “A 0.24-μm 2.0-V 1T1MTJ 15-kb Non-volatile Magnetoresistance RAM With Self-Reference Sensing Scheme,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 11, pp. 1906-1910, Nov., 2003.

[4] H. Tanizaki, et al, “A high-density and high-speed 1T-4MTJ MRAM with Voltage Offset Self-Reference Sensing Scheme,” Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian, 13-15, pp. 303-306, Nov., 2006.

[5] Y. Chen, et al, “Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM,” Symposium on Low Power Electronics and Design, ISLPED 2010, IEEE International, pp. 1-6, Aug., 2010

[6] H. Zhao, et al, “Low writing energy and sub nanosecond spin torque transfer switching of in-plane magnetic tunnel junction for spin torque transfer random access memory”, Journal of Applied Physics, 2011, Vol. 109, No. 7, 07C720, pp.1-3, Apr., 2011

[7] Z. Diao, et al, “Spin-transfer torque switching in magnetic tunnel junctions and spin-transfer torque random access memory,” Journal of Physics: Condensed Matter, 2007, Vol. 19, No. 16, 165209, pp. 1-13, Apr., 2007

[8] S. Ikeda, et al, “A Perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction,” Nature materials, 2010, Vol. 9, pp. 721-724, Sep., 2010.

Jun-Tae Choi received the B.S. in Department of Electronics and Infor- mation System Engineering and M.S. degrees in the Department of Elec- tronics and Computer Engineering from Hanyang University, Seoul, Korea, in 2012 and 2015, respect-

tively. He is currently pursuing the Ph. D. degree in Department of Electronics and Computer Engineering from Hanyang University, Korea. His interests include MRAM peri circuits, MTJ device,non-volatile SRAM and CMUT sensor.

Gyu-Hyun Kil received the B.S., M.S. and Ph. D degrees in the Department of Electronics and Computer Engineering from Han- yang University, Seoul, Korea, in 2009 and 2011, respectively. He is currently pursuing the Ph. D. degree

in Department of Electronics and Computer Engineering from Hanyang University, Korea. His interests include MRAM peri circuits, MTJ device and non-volatile SRAM.

38 JUN-TAE CHOI et al : NOVEL SELF-REFERENCE SENSE AMPLIFIER FOR SPIN-TRANSFER-TORQUE MAGNETO-RESISTIVE …

Kyu-beom Kim received the B.S. degrees in mathematics and electro- nics engineering and the M.S. degree in electronics engineering from Hanyang University, Seoul, South Korea, in 2010 and 2012, respec- tively. He is currently pursuing the

Ph.D. degree in electronics engineering at Hanyang University, Seoul, South Korea. His current research interests include MTJ device and biosensor for cancer detection/diagnosis.

Yun-heub Song received the B.S. degree in electronics engineering from Kyungpook National University, Daegu, South Korea, in 1984, the M.S. degree in electronics engineering from Hanyang University, Seoul, South Korea, in 1992 and the Ph.D.

degree in electrical engineering from Tohoku University, Sendai, Japan in 1999. In 1983, he was with Samsung Electronics Corporation, Ltd., Hwasung, South Korea, where he has been involved in process integration for erasable programmable read-only memory. From 1989 to 1995, he was a Technical Leader for process integration for low-power SRAM and CPU devices. After he received the Ph.D. degree in 1999, he rejoined Samsung Electronics Corporation, Ltd. and worked as a Project Manager (1999-2007) and a Vice President (2007-2008) for the process integration and device development for Flash memory in the Semiconductor R&D Center. In 2008, he joined Hanyang University as an Associate Professor, and became a Professor of department of Electronics and Computer Engineering, Hanyang University in 2014. He is the author of more than 25 articles and more than 40 inventions. His research interests include 3D crossbar array architecture, selective device, switching device, MTJ reliability for STT-MRAM, 3D-Vertical NAND Flash, 3D-PCRAM with synapse, CMOS logic device, biosensor, controlling surface tension, etc.